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TPS23757
SLVS948D – JULY 2009 – REVISED NOVEMBER 2013
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BLNK
Blanking provides an interval between GATE going high and the current-control comparators on CS actively
monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the
comparators are active, preventing undesired short duty cycles and premature current limiting.
Connect BLNK to ARTN to obtain the internally set blanking period. Connect a resistor from BLNK to ARTN for a
more accurate, programmable blanking period. The relationship between the desired blanking period and the
programming resistor is defined by Equation 2 .
R BLNK ( k W ) = t BLNK ( ns )
(2)
Place the resistor adjacent to the BLNK pin when it is used.
CLS
A resistor from CLS (class) to V SS programs the classification current per the IEEE standard. The PD power
ranges and corresponding resistor values are listed in Table 1 . The power assigned should correspond to the
maximum average power drawn by the PD during operation.
Table 1. Class Resistor Selection
CLASS
POWER AT PD
MINIMUM MAXIMUM
(W) (W)
RESISTOR
( ? )
NOTES
0
1
2
3
4
0.44
0.44
3.84
6.49
13
13
3.84
6.49
13
25.5
1270
243
137
90.9
63.4
Minimum may be reduced by pulsed loading. Serves as a catch-all default class.
Not allowed prior to IEEE 802.3at. Maximum type 2 hardware class current levels
not supported by TPS23757.
CS
The CS (current sense) input for the dc/dc converter should be connected to the high side of the switching
MOSFET’s current sense resistor (R CS ). The current-limit threshold, V CSMAX , defines the voltage on CS above
which the GATE ON time will be terminated regardless of the voltage on CTL.
The TPS23757 provides internal slope compensation (155 mV, V SLOPE ), an output current for additional slope
compensation, a peak current limiter, and an off-time pull-down to this pin.
Routing between the current-sense resistor and the CS pin should be short to minimize cross-talk from noisy
traces such as the gate drive signal.
CTL
CTL (control) is the voltage-control loop input to the PWM (pulse width modulator). Pulling V CTL below V ZDC (zero
duty cycle voltage) causes GATE to stop switching. Increasing V CTL above V ZDC raises the switching MOSFET
programmed peak current. The maximum (peak) current is requested at approximately V ZDC + (2 × V CSMAX ). The
ac gain from CTL to the PWM comparator is 0.5. The internal divider from CTL to ARTN is approximately 100
k ? .
Use V B as a pull up source for CTL.
DEN
DEN (detection and enable) is a multifunction pin for PoE detection and inhibiting operation from PoE power.
Connect a 24.9 k ? resistor from DEN to V DD to provide the PoE detection signature. DEN goes to a high-
impedance state when V VDD -V VSS is outside of the detection range. Pulling DEN to V SS during powered operation
causes the internal hotswap MOSFET and class regulator to turn OFF, while the reduced detection resistance
prevents the PD from properly re-detecting. See Using DEN to Disable PoE .
8
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